Computer Architecture MCQs
The Computer Architecture MCQ section on ExamVibe is designed for students, competitive exam aspirants, and computer science learners who want to strengthen their understanding of computer organization and hardware fundamentals. This category includes a wide collection of multiple-choice questions covering important topics such as CPU architecture, memory hierarchy, instruction sets, pipelining, input-output organization, cache memory, addressing modes, registers, and processor design.
Our expertly curated MCQs help learners prepare effectively for competitive exams like GATE, UGC NET, SSC, Banking, Railway, university examinations, and technical interviews. Each question is created to improve conceptual clarity, logical thinking, and problem-solving skills while matching current exam patterns and syllabus requirements.
With regularly updated content, detailed practice sets, and exam-oriented questions, the Computer Architecture MCQ category provides a reliable platform for mastering core computer science concepts and improving technical knowledge through smart learning.
Q1. What is computer architecture?
A. a) Physical components of a computer
B. b) Functional behavior and design of a computer system
C. c) Only software structure
D. d) Network topology
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Q2. Which unit performs arithmetic and logical operations?
A. a) Control Unit
B. b) Memory Unit
C. c) ALU
D. d) Cache
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Q3. Which memory is the fastest?
A. a) RAM
B. b) ROM
C. c) Cache Memory
D. d) Hard Disk
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Q5. Which bus carries memory addresses?
A. a) Data Bus
B. b) Control Bus
C. c) Address Bus
D. d) System Bus
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Q6. DMA stands for:
A. a) Direct Memory Access
B. b) Dynamic Memory Allocation
C. c) Direct Machine Access
D. d) Data Memory Allocation
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Q7. In pipelining, multiple instructions are:
A. a) Ignored
B. b) Executed simultaneously in different stages
C. c) Stored permanently
D. d) Converted to machine code
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Q8. Which is NOT a pipeline hazard?
A. a) Structural Hazard
B. b) Data Hazard
C. c) Control Hazard
D. d) Memory Hazard
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Q9. Virtual memory is mainly used to:
A. a) Increase CPU speed
B. b) Increase storage capacity
C. c) Extend main memory using secondary storage
D. d) Reduce cache size
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Q10. Which register stores the address of the next instruction?
A. a) MAR
B. b) MDR
C. c) PC
D. d) IR
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Q11. Cache memory is placed between:
A. a) CPU and RAM
B. b) RAM and ROM
C. c) Hard disk and CPU
D. d) ALU and CU
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Q12. Which addressing mode contains operand value directly?
A. a) Immediate Addressing
B. b) Direct Addressing
C. c) Indirect Addressing
D. d) Indexed Addressing
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Q13. The instruction cycle consists of:
A. a) Fetch and Execute
B. b) Read and Write
C. c) Input and Output
D. d) Decode only
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Q15. A data bus is:
A. a) Unidirectional
B. b) Bidirectional
C. c) Only input
D. d) Only output
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Q16. Which component controls all operations of the CPU?
A. a) ALU
B. b) CU
C. c) Register
D. d) Cache
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Q17. Which memory hierarchy level has the largest capacity?
A. a) Registers
B. b) Cache
C. c) Main Memory
D. d) Secondary Storage
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Q18. Which of the following is an example of secondary memory?
A. a) Cache
B. b) RAM
C. c) SSD
D. d) Register
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Q19. What is the main purpose of pipelining?
A. a) Reduce memory size
B. b) Increase instruction throughput
C. c) Increase power consumption
D. d) Reduce cache memory
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Q20. Which addressing mode uses a register to hold operand address?
A. a) Register Indirect
B. b) Immediate
C. c) Direct
D. d) Relative
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Q21. Interrupts are used to:
A. a) Stop CPU permanently
B. b) Improve graphics
C. c) Handle urgent tasks
D. d) Increase ROM size
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Q22. Which register stores the current instruction?
A. a) PC
B. b) IR
C. c) ACC
D. d) MAR
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Q23. Stack organization works on:
A. a) FIFO
B. b) LIFO
C. c) Random Access
D. d) Sequential Access
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Q24. Which processor is designed for parallel data operations?
A. a) Scalar Processor
B. b) Vector Processor
C. c) Serial Processor
D. d) Analog Processor
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Q25. Parallel processing improves:
A. a) Execution speed
B. b) Power loss
C. c) Virus protection
D. d) File size
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Q26. Associative memory is also known as:
A. a) Virtual Memory
B. b) Cache Memory
C. c) Content Addressable Memory
D. d) Optical Memory
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Q27. Which instruction transfers control to another location?
A. a) ADD
B. b) MOV
C. c) JUMP
D. d) STORE
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Q28. Which bus carries control signals?
A. a) Address Bus
B. b) Data Bus
C. c) Control Bus
D. d) Memory Bus
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Q29. The process of transferring data directly between I/O and memory is:
A. a) Interrupt
B. b) Polling
C. c) DMA
D. d) Caching
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Q30. Which memory is closest to CPU?
A. a) Hard Disk
B. b) Cache
C. c) RAM
D. d) Optical Disk
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Q31. Which type of hazard occurs due to branch instructions?
A. a) Structural Hazard
B. b) Data Hazard
C. c) Control Hazard
D. d) Arithmetic Hazard
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Q32. The number of bits processed by CPU at once is called:
A. a) Clock Rate
B. b) Word Length
C. c) Bus Width
D. d) Cache Size
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Q33. Which addressing mode is commonly used in loops?
A. a) Immediate
B. b) Relative
C. c) Direct
D. d) Indirect
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Q34. The MAR register stores:
A. a) Data
B. b) Instruction
C. c) Memory Address
D. d) Opcode
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Q35. Which device manages communication between CPU and peripherals?
A. a) I/O Interface
B. b) Cache
C. c) ALU
D. d) Register
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